Roa Logic’s General Manager, Richard Herveille, presented the company’s involvement and current development of a Platform-Level Interrupt Controller (PLIC) at the 7th RISC-V workshop. Read More
Support of five major vendors demonstrates growing strength of RISC-V ecosystemUltraSoC, the leading developer of embedded analytics technology, today announced that it has developed processor trace support for products based on the open source RISC-V architecture. The company has developed a specification for processor trace that will be offered for adoption by the RISC-V Foundation
Roa Logic’s General Manager, Richard Herveille, presented the company’s involvement and current development of RISC-V compatible CPUs at the 3rd RISC-V workshop. Scroll down or click here to watch the full video recording of the presentation.
Roa Logic joined the newly formed RISC-V foundation as one of its founding members. RISC-V (www.riscv.org) is a new open-standard Instruction Set Architecture on which all of Roa Logic’s CPUs are based. As a founding member Roa Logic has voting rights on future development of the ISA, which ensures that our customers’ interests are served
We finally got our webpage up and running (well almost). We will be adding content and our IP Portfolio in the coming weeks. Do not hesitate to contact us for enquiries. Cheers, The Roa Logic Team
About Roa LogicRoa Logic is your one stop shop for FPGA and ASIC design services.Roa Logic provides optimized, flexible IP solutions. All IP is silicon proven and supports both FPGA and ASIC implementations. All IP comes packed with a full featured testbench and documentation. In addition we provide custom solutions on request.Most of our IPs