Universal JTAG TAP Controller

DescriptionThe RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing


Repositories RISC CPU Cores RISC-V CPU Core https://github.com/RoaLogic/RV12 48 forks. 243 stars. 5 open issues. Recent commits: Updated bubble, Richard Herveille Fixed retired, Richard Herveille No retire on exceptions, Richard Herveille Added voptargs=+acc, Richard Herveille Updated minstret, Richard Herveille AMBA Peripherals https://github.com/RoaLogic/AMBA Memory IP Generic memory implementations https://github.com/RoaLogic/memory 11 forks. 8 stars. 1 open issues.