RV12 RISC-V Processor
Single-core RV32I, RV64I compliant RISC CPU based on the industry standard RISC-V instruction, for the embedded market.
Platform-Level Interrupt Controller (PLIC)
Fully parameterised and configurable RISC-V compliant Platform Level Interrupt Controller (PLIC)
Universal JTAG TAP Controller
DescriptionThe RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing
Github
Repositories RISC CPU Cores RISC-V CPU Core https://github.com/RoaLogic/RV12 48 forks. 243 stars. 5 open issues. Recent commits: Updated bubble, Richard Herveille Fixed retired, Richard Herveille No retire on exceptions, Richard Herveille Added voptargs=+acc, Richard Herveille Updated minstret, Richard Herveille AMBA Peripherals https://github.com/RoaLogic/AMBA Memory IP Generic memory implementations https://github.com/RoaLogic/memory 11 forks. 8 stars. 1 open issues.
GNU Eclipse Plugin
GNU Eclipse Plugin
GNU Eclipse Plugin
GNU Eclipse Plugin
AHB-Lite APB4 Bridge
Parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protocols
AHB-Lite Multilayer Switch
High Performance, Low Latency AHB-Lite Interconnect Fabric supporting an unlimited number of Bus Masters and Slaves
APB4 Multiplexer
Multiplexer enabling a single APB4 Master to communicate with multiple APB4 Slaves (Peripherals) via a common bus
AHB-Lite Memory
Fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master.
APB4 GPIO
Fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design
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