Universal JTAG TAP Controller

DescriptionThe RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing

Github

Repositories RISC CPU Cores RISC-V CPU Core https://github.com/RoaLogic/RV12 41 forks. 189 stars. 8 open issues. Recent commits: cleanup, Richard Herveille Fixed missing stall, Richard Herveille Fixed PMP_CNT sized ports, Richard Herveille New INV_RDCLK parameterNew logo and disclaimer, Richard Herveille New logo & disclaimer, Richard Herveille AMBA Peripherals https://github.com/RoaLogic/AMBA Memory IP Generic memory implementations https://github.com/RoaLogic/memory 10