Universal JTAG TAP Controller

DescriptionThe RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing

Github

Repositories RISC CPU Cores RISC-V CPU Corehttps://github.com/RoaLogic/RV1233 forks.146 stars.3 open issues.Recent commits: Quartus updates, Richard Herveille Updated functions, Richard Herveille removed superfluous signals, Richard Herveille Added bit-width to fsm_state, Richard Herveille Updated WAYS check, Richard Herveille AMBA Peripherals https://github.com/RoaLogic/AMBA Memory IP Generic memory implementationshttps://github.com/RoaLogic/memory8 forks.4 stars.0 open issues.Recent commits: Fixed bugs, added almost_ ports, Richard