RISC-V CPU Core
https://github.com/RoaLogic/RV12
41 forks.
189 stars.
8 open issues.

Recent commits:

• cleanup, Richard Herveille
• Fixed missing stall, Richard Herveille
• Fixed PMP_CNT sized ports, Richard Herveille
• New INV_RDCLK parameterNew logo and disclaimer, Richard Herveille
• New logo & disclaimer, Richard Herveille

Platform Level Interrupt Controller
https://github.com/RoaLogic/plic
10 forks.
13 stars.
3 open issues.

Recent commits:

• Fixed apb_re, Richard Herveille
• Fixed clock & reset, Richard Herveille
• Changed filename, Richard Herveille
• Fix link to RISC-V Specifications, GitHub
• Version 1.1 ReleaseMerge branch 'Docs/Rev1.1'* Docs/Rev1.1: Update PLIC to Privileged Spec 1.10 Compliance Correct width of ID register, Paul H