RISC-V CPU Core
https://github.com/RoaLogic/RV12
45 forks.
204 stars.
4 open issues.

Recent commits:

• cleanup, Richard Herveille
• Fixed missing stall, Richard Herveille
• Fixed PMP_CNT sized ports, Richard Herveille
• New INV_RDCLK parameterNew logo and disclaimer, Richard Herveille
• New logo & disclaimer, Richard Herveille

Platform Level Interrupt Controller
https://github.com/RoaLogic/plic
11 forks.
15 stars.
3 open issues.

Recent commits:

• Reset rdata, Richard Herveille
• Fixed apb_re, Richard Herveille
• Fixed clock & reset, Richard Herveille
• Changed filename, Richard Herveille
• Fix link to RISC-V Specifications, GitHub