RISC-V CPU Core
https://github.com/RoaLogic/RV12
34 forks.
155 stars.
5 open issues.
Recent commits:

• Quartus updates, Richard Herveille
• Updated functions, Richard Herveille
• removed superfluous signals, Richard Herveille
• Added bit-width to fsm_state, Richard Herveille
• Updated WAYS check, Richard Herveille

Platform Level Interrupt Controller
https://github.com/RoaLogic/plic
7 forks.
12 stars.
2 open issues.
Recent commits:

• Fix link to RISC-V Specifications, GitHub
• Version 1.1 ReleaseMerge branch 'Docs/Rev1.1'* Docs/Rev1.1: Update PLIC to Privileged Spec 1.10 Compliance Correct width of ID register, Paul H
• Update PLIC to Privileged Spec 1.10 Compliance, Paul H
• Correct width of ID register- Width should be clog2(SOURCES+1) to accommodate ID=0 → No IRQ Pending, Paul H
• Removed swap file, Richard Herveille