RISC-V CPU Core
https://github.com/RoaLogic/RV12
49 forks.
258 stars.
5 open issues.

Recent commits:

• Added voptargs, Richard Herveille
• Updated adr_o, Richard Herveille
• enwrapped RSB logger in ifdef, Richard Herveille
• Updated RSB, Richard Herveille
• Added RSB logger, Richard Herveille

Platform Level Interrupt Controller
https://github.com/RoaLogic/plic
13 forks.
27 stars.
5 open issues.

Recent commits:

• Moved import, Richard Herveille
• Reset rdata, Richard Herveille
• Fixed apb_re, Richard Herveille
• Fixed clock & reset, Richard Herveille
• Changed filename, Richard Herveille