Repositories
RISC CPU Cores
RISC-V CPU Core
https://github.com/RoaLogic/RV12
34 forks.
155 stars.
5 open issues.
Recent commits:
- Quartus updates, Richard Herveille
- Updated functions, Richard Herveille
- removed superfluous signals, Richard Herveille
- Added bit-width to fsm_state, Richard Herveille
- Updated WAYS check, Richard Herveille
AMBA Peripherals
https://github.com/RoaLogic/AMBA
Memory IP
Generic memory implementations
https://github.com/RoaLogic/memory
8 forks.
4 stars.
0 open issues.
Recent commits:
- Fixed bugs, added almost_ ports, Richard Herveille
- Removed 're_i' port from generic version, Richard Herveille
- Fixed queue_data write, Richard Herveille
- Fixed 'be_i' name, Richard Herveille
- Fixed typo, Richard Herveille