Repositories
RISC CPU Cores
RISC-V CPU Core
https://github.com/RoaLogic/RV12
48 forks.
214 stars.
4 open issues.
Recent commits:
- cleanup, Richard Herveille
- Fixed missing stall, Richard Herveille
- Fixed PMP_CNT sized ports, Richard Herveille
- New INV_RDCLK parameterNew logo and disclaimer, Richard Herveille
- New logo & disclaimer, Richard Herveille
AMBA Peripherals
https://github.com/RoaLogic/AMBA
Memory IP
Generic memory implementations
https://github.com/RoaLogic/memory
12 forks.
7 stars.
1 open issues.
Recent commits:
- Merge pull request #5 from RoaLogic/d2updateRemove duplicate port definition, GitHub
- Remove duplicate port definitionRdClock is declared twice and causes synthesis to fail – removed dupicate definition, Paul H
- Added RW_CONTENTION parameter, Richard Herveille
- Initial commit, Richard Herveille
- Fixed parameters, Richard Herveille