Repositories
RISC CPU Cores
RISC-V CPU Core
https://github.com/RoaLogic/RV12
48 forks.
243 stars.
5 open issues.
Recent commits:
- Updated bubble, Richard Herveille
- Fixed retired, Richard Herveille
- No retire on exceptions, Richard Herveille
- Added voptargs=+acc, Richard Herveille
- Updated minstret, Richard Herveille
AMBA Peripherals
https://github.com/RoaLogic/AMBA
Memory IP
Generic memory implementations
https://github.com/RoaLogic/memory
11 forks.
8 stars.
1 open issues.
Recent commits:
- Merge pull request #5 from RoaLogic/d2updateRemove duplicate port definition, GitHub
- Remove duplicate port definitionRdClock is declared twice and causes synthesis to fail – removed dupicate definition, Paul H
- Added RW_CONTENTION parameter, Richard Herveille
- Initial commit, Richard Herveille
- Fixed parameters, Richard Herveille