Single-core RV32I, RV64I compliant RISC CPU based on the industry standard RISC-V instruction, for the embedded market.
Fully parameterised and configurable RISC-V compliant Platform Level Interrupt Controller (PLIC)
Parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA APB v2.0 bus protocols
High Performance, Low Latency AHB-Lite Interconnect Fabric supporting an unlimited number of Bus Masters and Slaves
Multiplexer enabling a single APB4 Master to communicate with multiple APB4 Slaves (Peripherals) via a common bus
Fully parameterized soft IP implementing on-chip memory for access by an AHB-Lite based Master.
Fully parameterised core designed to provide a user-defined number of general purpose, bidirectional IO to a design
Timer module compliant the RISC-V Privileged 1.9.1 specification.
A full implementation of the 8b10b Widmer and Franaszek scheme, detects special commas and automatically detects K28.5.